Method for fabricating a semiconductor structure

ABSTRACT

A method for fabricating a semiconductor structure is disclosed. The method includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; and performing a second trimming process on at least the dielectric layer, wherein the second trimming process comprises trimming greater than 70% of a total trimming value.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation application of U.S. patent application Ser. No.12/851,550, filed on Aug. 5, 2010, and all benefits of such earlierapplication are hereby claimed for this new continuation application.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method for fabricating a semiconductorstructure, and more particularly, to a method of trimming hard mask forforming a gate electrode layer of a MOS structure.

2. Description of the Prior Art

During the process of manufacturing metal oxide semiconductortransistors (MOS transistors), the formation of a conductive gate playsan important role. In order to meet the demand of miniaturization of thesemiconductor industry, the current channel length under the gate mustmeet the standard of less than 35 nm. To meet the less than 35 nmchannel length requirement, it is crucial to control the criticaldimension (CD) during the process of exposure of the gate so as tocontrol the line width of the conductive layer (poly-Si layer forexample) after the etching process. Because the current lithographictool techniques are incapable of obtaining the ideal CD, trimmingmethods are employed in some prior art methods to reduce the size ofgate line width. However, most photo resist layers useful in the currentgate exposure process are 193 nm photo resist layers which areintrinsically less resistant to the etching condition than 365 nm photoresist layers are on account of acrylic and cycloalkenyl polymercomposition in contrast to 365 nm photo resist layers composed of arylmoiety. Furthermore, the thickness of 193 nm photo resist layers reducesas the exposure wavelength shortens. Under the dual disadvantages ofpoor etching resistance and less and less thickness, it is hard for 193nm photo resist layers to meet the minimum requirement of 30 nm owing tothe available thickness being 10 nm or less during the trimming processon 193 nm photo resist layers.

In order to overcome the problem, the current techniques deals with theproblems by transferring the pattern on the photo resist layer to thehard mask beneath the photo resist layer. After being patterned, thehard mask is ready for the trimming process to reduce the gate linewidth. In addition, the hard mask must have high etching selectivity tothe conductive layer used in forming gate layer. Accordingly, thetrimmed hard mask is ready to be the template for etching transferprocess to define the line width of gate layer.

However, as only one trimming process is typically employed on the photoresist layer and the hard mask above the designated gate layer, issuessuch as line twisting or line less often occur on the hard mask beneaththe photo resist layer and result in a flawed gate structure. Moreover,the hard mask is also prone to line collapse during the trimmingprocedure and the following etching on conductive layer, which woulddestroy the entire process or the results. Accordingly, it is importantto develop a better method for trimming hard masks to form the gate ofMOS transistors with ideal gate length.

SUMMARY OF THE INVENTION

It is an objective of the present invention to provide a method oftrimming hard masks for fabricating a gate layer of a MOS device.

According to a preferred embodiment of the present invention, a methodfor fabricating a semiconductor structure is disclosed. The methodincludes the steps of: providing a substrate; depositing a materiallayer on the substrate; forming at least one dielectric layer on thematerial layer; forming a patterned resist on the dielectric layer;performing a first trimming process on at least the patterned resist;performing a second trimming process on at least the dielectric layer;and using the dielectric layer as mask for etching the material layer.

Another aspect of the present invention discloses a method forfabricating a semiconductor structure, which includes the steps of:providing a substrate; depositing a material layer on the substrate;forming at least one dielectric layer on the material layer; forming apatterned resist on the dielectric layer; performing a first trimmingprocess on at least the patterned resist; and performing a secondtrimming process on at least the dielectric layer, wherein the secondtrimming process comprises trimming greater than 70% of a total trimmingvalue.

Another aspect of the present invention discloses a method forfabricating a semiconductor structure, which includes the steps of:providing a substrate; depositing a material layer on the substrate;forming a plurality of trimming layers on the material layer; andperforming at least a two-step trimming process on the trimming layerssuch that the trimming layers are trimmed twice.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-4 illustrate a method for fabricating a semiconductor structureaccording to a preferred embodiment of the present invention.

FIGS. 5-8 illustrate a method for fabricating a semiconductor structureaccording to an embodiment of the present invention.

DETAILED DESCRIPTION

Referring to FIGS. 1-4, FIGS. 1-4 illustrate a method for fabricating asemiconductor structure according to a preferred embodiment of thepresent invention. As shown in FIG. 1, a substrate 12, such as a siliconsubstrate is provided. Next, a gate dielectric layer (not shown)preferably composed of oxide, oxy-nitride, nitrogen-containingdielectric materials or a combination thereof may be formed on thesubstrate by thermal oxidation, chemical vapor deposition (CVD), orplasma enhanced chemical vapor deposition (PECVD). A material layer,such as a silicon layer or a polysilicon layer 14 is then deposited onthe gate dielectric layer and at least a dielectric layer 16 is formedon the polysilicon layer 14 thereafter.

The at least one dielectric layer 16 may be composed of one singledielectric layer or a plurality of dielectric layers. In thisembodiment, a plurality of dielectric layers are deposited on thepolysilicon layer 14, in which the dielectric layers include a hard mask18 and a bottom anti-reflective coating (BARC) 20. In this embodiment,the hard mask 18 could be selected from a material consisting of SiON,SiO₂, TEOS, or a combination thereof, and the BARC 20 may be formed froman organic polymer anti-reflective coating material, such as a 365 nm(I-line) resist layer. A patterned resist 22 is formed on the BARC 20thereafter.

After the patterned resist 22 is formed, a trimming process 24 could beconducted to narrow the width of the patterned resist 22. The trimmingprocess 24 may be accomplished by a plasma etch using gases such asoxygen, ozone, CF₄, CHF₃ or HBr/O₂, and if the target layer to betrimmed were resist material, ashing may be used.

As shown in FIG. 2, after trimming the patterned resist 22, an etchingprocess is carried out by using the patterned resist as mask to remove aportion of the BARC 20 underneath. After the pattern of the patternedresist 22 is transferred to the BARC 20, another trimming process 26 isconducted to narrow the width of the patterned resist 22 and the BARC20. The etching gas used in this trimming process 26 preferably trimsonly the target layers such as the aforementioned patterned resist 22and BARC 20 without affecting any other layer underneath, and could beidentical or different from the etching gas used in the previoustrimming step 24.

As shown in FIG. 3, after the patterned resist 22 and the BARC 20 aretrimmed, an etching is performed by using the patterned resist 22 andthe BARC 20 as mask to remove a portion of the hard mask 18 underneath.As the etching is carried out on the hard mask 18, a portion of thepolysilicon layer 14 surface is exposed and the patterned resist 22 maybe etched away as the pattern of the BARC 20 is transferred to the hardmask 18. Next, another trimming process 28 could be conducted to narrowthe width of the BARC 20 and the hard mask 18. The etching gas used inthis trimming process 28 could be identical or different from theetching gas used in the previous trimming steps 24 or 26.

Preferably, as a substantial amount of polysilicon layer 14 is lost dueto the etching gas used during the trimming procedure, a fixed time wereto be calculated for the trimming process 28 after exposing thepolysilicon layer 14 to control the width difference between the top ofthe polysilicon layer 14 and the bottom of the polysilicon layer 14 nomore than 10%. According to a preferred embodiment of the presentinvention, the fixed time of the trimming procedure is calculated aftertrimming greater than 70% of a total trimming value.

For instance, if a width of the BARC 20 and the hard mask 18 were to bereduced from 60 nm to 40 nm after the surface of the polysilicon layer14 is exposed, 6 nm from the total of 20 nm being etched away in thetrimming procedure would be reserved for the polysilicon layer 14. Asthe trimming procedure starts, a fixed time of 30 seconds is calculatedto trim the 6 nm for the polysilicon layer 14.

It should be noted that even though three trimming processes 24, 26, 28are disclosed in this embodiment, operators could choose to perform onlytwo or all three of these trimming process 24, 26, 28 through thefabrication.

For instance, if only the trimming processes 26 and 28 were selected tobe performed throughout the fabrication, operators could omit thetrimming process 24 by using the un-trimmed patterned resist 22 directlyas mask to pattern the BARC 20 and perform the subsequent trimmingprocesses 26 and 28 as mentioned previously.

Moreover, despite the aforementioned embodiment strips the patternedresist 22 after the trimming process 26 by either a separate etchingprocess or along with the patterning of the hard mask 18, the patternedresist 22 could also be remained on the BARC 20 and the hard mask 18until exposing the surface of the polysilicon layer 14. In other words,after trimming the patterned resist 22, one ore more etching processcould be carried by using the patterned resist 22 as mask to pattern theBARC 20 and hard mask 18 until exposing the surface of the polysiliconlayer 14. After the polysilicon layer 14 is exposed, another trimmingprocess is conducted to trim the patterned resist 22, the patterned BARC20, and the patterned hard mask 18 before patterning the polysiliconlayer 14. This approach of performing at least two trimming process thatall involves the trimming of patterned resist is also within the scopeof the present invention.

As shown in FIG. 4, after the patterned BARC 20 and the hard mask 18 aretrimmed, an etching is performed by using the patterned BARC 20 and thehard mask 18 as mask to remove a portion of the polysilicon layer 14underneath for forming a patterned polysilicon layer 14. The patternedpolysilicon layer 14 is preferably used as a gate electrode of ametal-oxide semiconductor (MOS) device, and after the patternedpolysilicon 14 is formed, typical MOS fabrication involving theformation of offset spacer, lightly doped drain, main spacer,source/drain region, epitaxial layers, stress layers, salicides, andcontact plugs could be employed to form a MOS structure. As thefabrication of these MOS structure elements are commonly known to thoseskilled in the art in this field, the details of which are omittedherein for the sake of brevity.

In another embodiment of the present invention, the material layer caninclude other suitable materials, such as silicon, silicon oxide ormetal. Therefore, the patterned material layer fabricated by abovementioned steps can be used as other semiconductor structure, such asSTI or contact plug.

Referring to FIGS. 5-8, FIGS. 5-8 illustrate a method for fabricating asemiconductor structure according to an embodiment of the presentinvention. As shown in FIG. 5, a substrate 42, such as a siliconsubstrate is provided. Next, a gate dielectric layer (not shown)preferably composed of oxide, oxy-nitride, nitrogen-containingdielectric materials or a combination thereof may be formed on thesubstrate by thermal oxidation, chemical vapor deposition (CVD), orplasma enhanced chemical vapor deposition (PECVD). A polysilicon layer44 is then deposited on the gate dielectric layer and at least adielectric layer 46 is formed on the polysilicon layer 44 thereafter.

The at least one dielectric layer 46 may be composed of one singledielectric layer or a plurality of dielectric layers. In thisembodiment, a plurality of dielectric layers are deposited on thepolysilicon layer 44, in which the dielectric layers include a hard mask48, an advanced patterning film (APF) 50 from Applied Materials, Inc.,and a dielectric anti-reflective coating (DARC) 52. In this embodiment,the hard mask 48 could be selected from a material consisting of SiON,SiO₂, TEOS, or a combination thereof, and the DARC 52 may be formed froman organic polymer anti-reflective coating material, such as asilicon-rich silicon oxynitride layer. A patterned resist 54 is formedon the DARC thereafter.

An etching is then carried out by using the patterned resist 54 as maskto remove a portion of the DARC 52 underneath for forming a patternedDARC 52. Despite the patterned resist 54 is used directly as an etchingmask for patterning the DARC 52 underneath, a trimming process could beconducted before the DARC 52 is etched. After the DARC 52 is patterned,a trimming process is conducted to narrow the width of the patternedresist 54 and the patterned DARC 52. The trimming process 56 may beaccomplished by a plasma etch using gases such as oxygen, ozone, CF₄,CHF₃ or HBr/O₂, and if the target layer to be trimmed were resistmaterial, ashing may be used.

As shown in FIG. 6, after trimming the patterned resist 54 and the DARC52, an etching process is carried out by using the patterned resist 54and DARC 52 as mask to remove a portion of the APF 50 underneath.Depending on the etchant used for removing the APF 50, the patternedresist 54 could be removed as the APF 50 is patterned, or could beremoved by a separate etching step prior to the patterning of the APF50, which is also within the scope of the present invention. After thepattern of the DARC 52 is transferred to the APF 50, another trimmingprocess 58 is conducted to narrow the width of the DARC 52 and the APF50. The etching gas used in this trimming process 58 could be identicalor different from the etching gas used in the previous trimming step 56.

As shown in FIG. 7, after trimming the patterned DARC 52 and the APF 50,an etching process is carried out by using the trimmed DARC 52 and APF50 as mask to remove a portion of the hard mask 48 underneath. Dependingon the etchant used for removing the hard mask 48, the DARC 52 could beremoved as the hard mask 48 is patterned, or could be removed by aseparate etching step prior to the patterning of the hard mask 48, whichis also within the scope of the present invention. After the pattern ofthe APF 50 is transferred to the hard mask 48, another trimming process60 is conducted to narrow the width of the APF 50 and the hard mask 48.The etching gas used in this trimming process 60 could be identical ordifferent from the etching gas used in the previous trimming steps 56 or58.

Similar to the aforementioned embodiment, even though three trimmingprocesses 56, 58, 60 are disclosed in this embodiment, operators couldchoose to perform only two or all three of these trimming process 56,58, 60 throughout the fabrication.

For instance, if only the trimming processes 58 and 60 were selected tobe performed throughout the fabrication, operators could omit thetrimming process 24 by using the un-trimmed patterned resist 54 and DARC52 directly as mask to pattern the APF 50 and perform the subsequenttrimming processes 58 and 60 as mentioned previously.

Moreover, despite the aforementioned embodiment strips the patternedresist 54 after the trimming process 56 by either a separate etchingprocess or along with the patterning of the APF 50, the patterned resist54 could also be remained on the DARC 52 until exposing the surface ofthe polysilicon layer 44. In other words, after trimming the patternedresist 54 and the DARC 52, one ore more etching process could be carriedby using the patterned resist 54 and DARC 52 as mask to pattern the APF50 and hard mask 48 until exposing the surface of the polysilicon layer44. After the polysilicon layer 44 is exposed, another trimming processis conducted to trim the patterned resist 54, the patterned DARC 52,patterned APF 50, and the patterned hard mask 48 before transferring thepattern to the polysilicon layer 44. This approach of performing atleast two trimming process that all involves the trimming of patternedresist is also within the scope of the present invention.

As shown in FIG. 8, after the patterned APF 50 and the hard mask 48 aretrimmed, an etching is performed by using the patterned APF 50 and thehard mask 48 as mask to remove a portion of the polysilicon layer 44underneath. The patterned APF 50 and the hard mask 48 could be removedby another etching thereafter.

The patterned polysilicon layer 44 is preferably used as a gateelectrode of a metal-oxide semiconductor (MOS) device, and after thepatterned polysilicon 44 is formed, typical MOS fabrication involvingthe formation of offset spacer, lightly doped drain, main spacer,source/drain region, epitaxial layers, salicides, and contact plugscould be employed to form a MOS structure. As the fabrication of theseMOS structure elements are commonly known to those skilled in the art inthis field, the details of which are omitted herein for the sake ofbrevity.

Overall, the present invention conducts at least two trimming processthrough the fabrication of a semiconductor structure, such as apolysilicon gate of a MOS device. By applying two or more trimmingprocess on the patterned resist and dielectric layers above thedesignated polysilicon layer, issued such as line lost or line collapseduring the trimming procedure of gate layer formation could be improvedsubstantially.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A method for fabricating a semiconductor structure, comprising thesteps of: providing a substrate; depositing a material layer on thesubstrate; forming at least one dielectric layer on the material layer;forming a patterned resist on the dielectric layer; performing a firsttrimming process on at least the patterned resist; and performing asecond trimming process on at least the dielectric layer, wherein thesecond trimming process comprises trimming greater than 70% of a totaltrimming value.
 2. The method of claim 1, wherein the material layercomprises silicon, polysilicon layer or metal.
 3. The method of claim 1,further comprising calculating a fixed time of the second trimmingprocess after trimming greater than 70% of the total trimming value. 4.The method of claim 1, wherein the at least one dielectric layercomprises a bottom anti-reflective coating (BARC) and a hard mask. 5.The method of claim 4, further comprising: performing the first trimmingprocess on the patterned resist; using the patterned resist for etchingthe BARC; performing the second trimming process on the patterned resistand the BARC; using the patterned resist and the BARC to etch the hardmask for exposing the material layer; performing a third trimmingprocess on the BARC and the hard mask; and using the BARC and the hardmask for etching the material layer.
 6. The method of claim 4, furthercomprising: performing the first trimming process on the patternedresist and the BARC; using the patterned resist and the BARC to etch thehard mask for exposing the material layer; performing the secondtrimming process on the BARC and the hard mask; and using the BARC andthe hard mask for etching the material layer.
 7. The method of claim 1,wherein the at least one dielectric layer comprises a dielectricanti-reflective coating (DARC), an advanced patterning film (APF), and ahard mask.
 8. The method of claim 7, further comprising: performing thefirst trimming process on the patterned resist and the DARC; using thepatterned resist and the DARC for etching the APF; performing the secondtrimming process on the DARC and the APF; and using the DARC and the APFto etch the hard mask for exposing the material layer; and performing athird trimming process on the APF and the hard mask; and using the APFand the hard mask for etching the material layer.
 9. The method of claim7, further comprising: performing the first trimming process on thepatterned resist and the DARC; using the patterned resist and the DARCfor etching the APF and the hard mask for exposing the material layer;performing the second trimming process on the APF and the hard mask; andusing the APF and the hard mask for etching the material layer.
 10. Themethod of claim 1, wherein the second trimming process is conductedaccording to a fixed time for controlling the width difference betweenthe top of the material layer and the bottom of the material layer nomore than 10%.
 11. The method of claim 1, wherein the second trimmingprocess is performed on at least the dielectric layer after exposing thematerial layer.
 12. A method for fabricating a semiconductor structure,comprising the steps of: providing a substrate; depositing a materiallayer on the substrate; forming at least one dielectric layer on thematerial layer; forming a patterned resist on the dielectric layer;performing a first trimming process on at least the patterned resist;and performing a second trimming process on at least the dielectriclayer after exposing the material layer.
 13. The method of claim 12,wherein the material layer comprises silicon, polysilicon layer ormetal.
 14. The method of claim 12 further comprising calculating a fixedtime of the second trimming process after trimming greater than 70% ofthe total trimming value.
 15. The method of claim 12, wherein the atleast one dielectric layer comprises a bottom anti-reflective coating(BARC) and a hard mask.
 16. The method of claim 15, further comprising:performing the first trimming process on the patterned resist; using thepatterned resist for etching the BARC; performing the second trimmingprocess on the patterned resist and the BARC; using the patterned resistand the BARC to etch the hard mask for exposing the material layer;performing a third trimming process on the BARC and the hard mask; andusing the BARC and the hard mask for etching the material layer.
 17. Themethod of claim 15, further comprising: performing the first trimmingprocess on the patterned resist and the BARC; using the patterned resistand the BARC to etch the hard mask for exposing the material layer;performing the second trimming process on the BARC and the hard mask;and using the BARC and the hard mask for etching the material layer. 18.The method of claim 12, wherein the at least one dielectric layercomprises a dielectric anti-reflective coating (DARC), an advancedpatterning film (APF), and a hard mask.
 19. The method of claim 18,further comprising: performing the first trimming process on thepatterned resist and the DARC; using the patterned resist and the DARCfor etching the APF; performing the second trimming process on the DARCand the APF; and using the DARC and the APF to etch the hard mask forexposing the material layer; and performing a third trimming process onthe APF and the hard mask; and using the APF and the hard mask foretching the material layer.
 20. The method of claim 18, furthercomprising: performing the first trimming process on the patternedresist and the DARC; using the patterned resist and the DARC for etchingthe APF and the hard mask for exposing the material layer; performingthe second trimming process on the APF and the hard mask; and using theAPF and the hard mask for etching the material layer.
 21. The method ofclaim 12, wherein the second trimming process is conducted according toa fixed time for controlling the width difference between the top of thematerial layer and the bottom of the material layer no more than 10%.